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CY28548
........................Document #: 001-08400 Rev ** Page 4 of 30
25
SRCC1 /
LCDC_100/27M_SS
O, DIF,
SE
Complementary 100 MHz differential serial reference clock output/Comple-
mentary 100 MHz LCD video clock output /Spread 27 MHz video clock output.
Selected via GCLK_SEL at CKPWRGD assertion.
26
VSS_PLL3
GND
Ground for PLL3.
27
VDD_PLL3_IO
PWR
3.3V-1.25V power supply for outputs.
28
SRCT2 / SATAT
O, DIF True 100 MHz differential serial reference clock output.
29
SRCC2 / SATAC
O, DIF Complementary 100 MHz differential serial reference clock output.
30
VSS_SRC
GND
Ground for outputs.
31
SRCT3 / CR#_C
I/O,
DIF
True 100 MHz differential serial reference clock output /3.3V Clock Request
#_C/D input
Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.
The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC
to stop when asserted
32
SRCC3 / CR#_D
I/O,
DIF
Complementary 100 MHz differential serial reference clock output/3.3V Clock
Request #_C/D input
Selected via CR#_C_EN/CR#_D_EN bit located in byte 5 bit 3and 1.
The CR#_C_SEL and CR#_D_SEL bits in byte 5 bit 2 and 0 will select which SRC
to stop when asserted
33
VDD_SRC_IO
PWR
3.3V-1.25V Power supply for outputs.
34
SRCT4
O, DIF True 100 MHz differential serial reference clocks.
35
SRCC4
O, DIF Complementary 100 MHz differential serial reference clocks.
36
VSS_SRC
GND
Ground for outputs.
37
SRCT9
O, DIF True 100 MHz differential serial reference clocks.
38
SRCC9
O, DIF Complementary 100 MHz differential serial reference clocks.
39
SRCC11/ CR#_G
I/O,
DIF
True 100 MHz differential serial reference clocks/3.3V CR#_G Input.
Selected via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
40
SRCT11/ CR#_H
I/O,
DIF
Complementary 100 MHz Differential serial reference clocks/3.3V CR#_H
Input.
Selected via CR#_G_EN/CR#_H_EN bit located in byte 6 bit 5 and 4.
When selected, CR#_G controls SRC9, CR#_H controls SRC10
41
SRCT10
O, DIF True 100 MHz Differential serial reference clocks.
42
SRCC10
O, DIF Complementary 100 MHz Differential serial reference clocks.
43
VDD_SRC_IO
PWR
3.3V-1.25V power supply for outputs.
44
CPU_STOP#
I
3.3V-tolerant input for stopping CPU outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 13
for more information.
45
PCI_STOP#
I
3.3V-tolerant input for stopping PCI and SRC outputs
During direct clock off to M1 mode transition, a serial load of BSEL data is driven
on CPU_STOP# and sampled on the rising edge of PCI_STOP#. See Figure 13
for more information.
46
VDD_SRC
PWR
3.3V power supply for SRC PLL.
47
SRCC6
O, DIF Complementary 100 MHz Differential serial reference clocks.
48
SRCT6
O, DIF True 100 MHz Differential serial reference clocks.
49
VSS_SRC
GND
Ground for outputs.
50
SRCC7/ CR#_E
I/O,
DIF
Complementary 100 MHz differential serial reference clocks/3.3V CR#_E
Input.
Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
QFN Pin Definitions (continued)
Pin No.
Name
Type
Description
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